METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects in...

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Hauptverfasser: LU WEI, CONG HAI, ZHOU MEI SHENG, HSIA LIANG CHOO, SEE ALEX KH, YE JIANHUI, KOH HUI PENG, LIU HUANG
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator LU WEI
CONG HAI
ZHOU MEI SHENG
HSIA LIANG CHOO
SEE ALEX KH
YE JIANHUI
KOH HUI PENG
LIU HUANG
description A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the propagation of surface defects into the substrate, thereby minimizing the occurrence of silicide pipe defects. The spacer pull-back etch can be performed after a first annealing step to form the silicide contacts.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
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