MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES
A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystall...
Gespeichert in:
Hauptverfasser: | , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | AGNELLO PAUL DAVID NARASIMHA SHREESH CHEN XIAOMENG KIM BYEONG Y HOLT JUDSON R SADANA DEVENDRA K KHARE MUKESH VIJAY |
description | A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010197118A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010197118A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010197118A13</originalsourceid><addsrcrecordid>eNrjZLDzDfUJ8QzwcVVwDooMDnH08fF3D3IM8PB0VvAP8nT1C3EM8fT3Uwh29fV09vdzCXUO8Q9SCA4JAjJCg1yDeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhgaGluaGhhaOhMXGqAHrELAs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES</title><source>esp@cenet</source><creator>AGNELLO PAUL DAVID ; NARASIMHA SHREESH ; CHEN XIAOMENG ; KIM BYEONG Y ; HOLT JUDSON R ; SADANA DEVENDRA K ; KHARE MUKESH VIJAY</creator><creatorcontrib>AGNELLO PAUL DAVID ; NARASIMHA SHREESH ; CHEN XIAOMENG ; KIM BYEONG Y ; HOLT JUDSON R ; SADANA DEVENDRA K ; KHARE MUKESH VIJAY</creatorcontrib><description>A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100805&DB=EPODOC&CC=US&NR=2010197118A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100805&DB=EPODOC&CC=US&NR=2010197118A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AGNELLO PAUL DAVID</creatorcontrib><creatorcontrib>NARASIMHA SHREESH</creatorcontrib><creatorcontrib>CHEN XIAOMENG</creatorcontrib><creatorcontrib>KIM BYEONG Y</creatorcontrib><creatorcontrib>HOLT JUDSON R</creatorcontrib><creatorcontrib>SADANA DEVENDRA K</creatorcontrib><creatorcontrib>KHARE MUKESH VIJAY</creatorcontrib><title>MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES</title><description>A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDzDfUJ8QzwcVVwDooMDnH08fF3D3IM8PB0VvAP8nT1C3EM8fT3Uwh29fV09vdzCXUO8Q9SCA4JAjJCg1yDeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhgaGluaGhhaOhMXGqAHrELAs</recordid><startdate>20100805</startdate><enddate>20100805</enddate><creator>AGNELLO PAUL DAVID</creator><creator>NARASIMHA SHREESH</creator><creator>CHEN XIAOMENG</creator><creator>KIM BYEONG Y</creator><creator>HOLT JUDSON R</creator><creator>SADANA DEVENDRA K</creator><creator>KHARE MUKESH VIJAY</creator><scope>EVB</scope></search><sort><creationdate>20100805</creationdate><title>MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES</title><author>AGNELLO PAUL DAVID ; NARASIMHA SHREESH ; CHEN XIAOMENG ; KIM BYEONG Y ; HOLT JUDSON R ; SADANA DEVENDRA K ; KHARE MUKESH VIJAY</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010197118A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AGNELLO PAUL DAVID</creatorcontrib><creatorcontrib>NARASIMHA SHREESH</creatorcontrib><creatorcontrib>CHEN XIAOMENG</creatorcontrib><creatorcontrib>KIM BYEONG Y</creatorcontrib><creatorcontrib>HOLT JUDSON R</creatorcontrib><creatorcontrib>SADANA DEVENDRA K</creatorcontrib><creatorcontrib>KHARE MUKESH VIJAY</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AGNELLO PAUL DAVID</au><au>NARASIMHA SHREESH</au><au>CHEN XIAOMENG</au><au>KIM BYEONG Y</au><au>HOLT JUDSON R</au><au>SADANA DEVENDRA K</au><au>KHARE MUKESH VIJAY</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES</title><date>2010-08-05</date><risdate>2010</risdate><abstract>A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device. An additional semiconductor structure includes a further laterally adjacent second semiconductor-on-insulator surface semiconductor layer having the first polarity and the second crystallographic orientation, and absent edge defects, to accommodate yield sensitive devices.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2010197118A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | MULTIPLE CRYSTALLOGRAPHIC ORIENTATION SEMICONDUCTOR STRUCTURES |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T23%3A19%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AGNELLO%20PAUL%20DAVID&rft.date=2010-08-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2010197118A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |