DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM

The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The depos...

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1. Verfasser:	FIORILLO ANTONINO SECONDO
Format:	Patent
Sprache:	eng
Schlagworte:	ADHESIVES BASIC ELECTRIC ELEMENTS CHEMICAL PAINT OR INK REMOVERS CHEMISTRY COATING COMPOSITIONS, e.g. PAINTS, VARNISHES ORLACQUERS CORRECTING FLUIDS DYES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FILLING PASTES INKS LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM METALLURGY MISCELLANEOUS APPLICATIONS OF MATERIALS MISCELLANEOUS COMPOSITIONS NATURAL RESINS PAINTS PASTES OR SOLIDS FOR COLOURING OR PRINTING PERFORMING OPERATIONS POLISHES SEMICONDUCTOR DEVICES TRANSPORTING USE OF MATERIALS THEREFOR WOODSTAINS
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creator	FIORILLO ANTONINO SECONDO
description	The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010117165A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010117165A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010117165A13</originalsourceid><addsrcrecordid>eNrjZIhycQ3wD_YM8fT3U_B3U_BxjHQNCgaxAvyD_EODFXwdQ1yDPB19gnVgciEeQGF_pxBHTz9XFwVHPxcFF9cwT2fXYAVnfz-QqKefO1CRqy8PA2taYk5xKi-U5mZQdnMNcfbQTS3Ij08tLkhMTs1LLYkPDTYyMDQwNDQ3NDN1NDQmThUAGFIymw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM</title><source>esp@cenet</source><creator>FIORILLO ANTONINO SECONDO</creator><creatorcontrib>FIORILLO ANTONINO SECONDO</creatorcontrib><description>The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning.</description><language>eng</language><subject>ADHESIVES ; BASIC ELECTRIC ELEMENTS ; CHEMICAL PAINT OR INK REMOVERS ; CHEMISTRY ; COATING COMPOSITIONS, e.g. PAINTS, VARNISHES ORLACQUERS ; CORRECTING FLUIDS ; DYES ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FILLING PASTES ; INKS ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; METALLURGY ; MISCELLANEOUS APPLICATIONS OF MATERIALS ; MISCELLANEOUS COMPOSITIONS ; NATURAL RESINS ; PAINTS ; PASTES OR SOLIDS FOR COLOURING OR PRINTING ; PERFORMING OPERATIONS ; POLISHES ; SEMICONDUCTOR DEVICES ; TRANSPORTING ; USE OF MATERIALS THEREFOR ; WOODSTAINS</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100513&DB=EPODOC&CC=US&NR=2010117165A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100513&DB=EPODOC&CC=US&NR=2010117165A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FIORILLO ANTONINO SECONDO</creatorcontrib><title>DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM</title><description>The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning.</description><subject>ADHESIVES</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CHEMICAL PAINT OR INK REMOVERS</subject><subject>CHEMISTRY</subject><subject>COATING COMPOSITIONS, e.g. PAINTS, VARNISHES ORLACQUERS</subject><subject>CORRECTING FLUIDS</subject><subject>DYES</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FILLING PASTES</subject><subject>INKS</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>METALLURGY</subject><subject>MISCELLANEOUS APPLICATIONS OF MATERIALS</subject><subject>MISCELLANEOUS COMPOSITIONS</subject><subject>NATURAL RESINS</subject><subject>PAINTS</subject><subject>PASTES OR SOLIDS FOR COLOURING OR PRINTING</subject><subject>PERFORMING OPERATIONS</subject><subject>POLISHES</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><subject>USE OF MATERIALS THEREFOR</subject><subject>WOODSTAINS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIhycQ3wD_YM8fT3U_B3U_BxjHQNCgaxAvyD_EODFXwdQ1yDPB19gnVgciEeQGF_pxBHTz9XFwVHPxcFF9cwT2fXYAVnfz-QqKefO1CRqy8PA2taYk5xKi-U5mZQdnMNcfbQTS3Ij08tLkhMTs1LLYkPDTYyMDQwNDQ3NDN1NDQmThUAGFIymw</recordid><startdate>20100513</startdate><enddate>20100513</enddate><creator>FIORILLO ANTONINO SECONDO</creator><scope>EVB</scope></search><sort><creationdate>20100513</creationdate><title>DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM</title><author>FIORILLO ANTONINO SECONDO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010117165A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>ADHESIVES</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CHEMICAL PAINT OR INK REMOVERS</topic><topic>CHEMISTRY</topic><topic>COATING COMPOSITIONS, e.g. PAINTS, VARNISHES ORLACQUERS</topic><topic>CORRECTING FLUIDS</topic><topic>DYES</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FILLING PASTES</topic><topic>INKS</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>METALLURGY</topic><topic>MISCELLANEOUS APPLICATIONS OF MATERIALS</topic><topic>MISCELLANEOUS COMPOSITIONS</topic><topic>NATURAL RESINS</topic><topic>PAINTS</topic><topic>PASTES OR SOLIDS FOR COLOURING OR PRINTING</topic><topic>PERFORMING OPERATIONS</topic><topic>POLISHES</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><topic>USE OF MATERIALS THEREFOR</topic><topic>WOODSTAINS</topic><toplevel>online_resources</toplevel><creatorcontrib>FIORILLO ANTONINO SECONDO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FIORILLO ANTONINO SECONDO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM</title><date>2010-05-13</date><risdate>2010</risdate><abstract>The present invention describes a process for the deposition of one or more layers of zeolites on rigid supports of various natures and geometry, particularly on silicon wafers. The coating containing zeolites is characterised by pore sizes ranging from 1 Angstrom to a few nanometer units. The deposition process does not interfere with and/or alter the correct functioning of the electronic devices (diodes, bipolar junction transistors, field effect transistors and electronic amplifiers in general) already integrated on the support to be coated on which said deposition is effected. The process according to the invention can be applied to electronic devices and permits their unaltered correct functioning.</abstract><oa>free_for_read</oa></addata></record>
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subjects	ADHESIVES BASIC ELECTRIC ELEMENTS CHEMICAL PAINT OR INK REMOVERS CHEMISTRY COATING COMPOSITIONS, e.g. PAINTS, VARNISHES ORLACQUERS CORRECTING FLUIDS DYES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FILLING PASTES INKS LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM METALLURGY MISCELLANEOUS APPLICATIONS OF MATERIALS MISCELLANEOUS COMPOSITIONS NATURAL RESINS PAINTS PASTES OR SOLIDS FOR COLOURING OR PRINTING PERFORMING OPERATIONS POLISHES SEMICONDUCTOR DEVICES TRANSPORTING USE OF MATERIALS THEREFOR WOODSTAINS
title	DEPOSITION OF LAYERS OF POROUS MATERIALS, LAYERS THUS OBTAINED AND DEVICES CONTAINING THEM
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