Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof

One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: GILMORE DAMIEN T, EUGEN MINDRICELU P, HU BINGHUA, WOFFORD BILL A
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator GILMORE DAMIEN T
EUGEN MINDRICELU P
HU BINGHUA
WOFFORD BILL A
description One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010001364A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010001364A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010001364A13</originalsourceid><addsrcrecordid>eNqNzLEKwjAQgOEuDqK-w4Gz0FpxF620Q3FoncuRXJpgmitJWvXtRfABnP7l418m74YGI9jJSUT2cKHZCIISZ-N6qIbR80wSbi8jCVptxMNRCIAREBqN1vITWk9OaKgCW4yGHRSyJ0AnoaaoWQIrqNFNCkWc_HdDnlitk4VCG2jz6yrZXov2XO5o5I7CiIIcxe7e7NMsTdMsPx5OWf6f-gCUskZ5</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof</title><source>esp@cenet</source><creator>GILMORE DAMIEN T ; EUGEN MINDRICELU P ; HU BINGHUA ; WOFFORD BILL A</creator><creatorcontrib>GILMORE DAMIEN T ; EUGEN MINDRICELU P ; HU BINGHUA ; WOFFORD BILL A</creatorcontrib><description>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100107&amp;DB=EPODOC&amp;CC=US&amp;NR=2010001364A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100107&amp;DB=EPODOC&amp;CC=US&amp;NR=2010001364A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GILMORE DAMIEN T</creatorcontrib><creatorcontrib>EUGEN MINDRICELU P</creatorcontrib><creatorcontrib>HU BINGHUA</creatorcontrib><creatorcontrib>WOFFORD BILL A</creatorcontrib><title>Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof</title><description>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzLEKwjAQgOEuDqK-w4Gz0FpxF620Q3FoncuRXJpgmitJWvXtRfABnP7l418m74YGI9jJSUT2cKHZCIISZ-N6qIbR80wSbi8jCVptxMNRCIAREBqN1vITWk9OaKgCW4yGHRSyJ0AnoaaoWQIrqNFNCkWc_HdDnlitk4VCG2jz6yrZXov2XO5o5I7CiIIcxe7e7NMsTdMsPx5OWf6f-gCUskZ5</recordid><startdate>20100107</startdate><enddate>20100107</enddate><creator>GILMORE DAMIEN T</creator><creator>EUGEN MINDRICELU P</creator><creator>HU BINGHUA</creator><creator>WOFFORD BILL A</creator><scope>EVB</scope></search><sort><creationdate>20100107</creationdate><title>Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof</title><author>GILMORE DAMIEN T ; EUGEN MINDRICELU P ; HU BINGHUA ; WOFFORD BILL A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010001364A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GILMORE DAMIEN T</creatorcontrib><creatorcontrib>EUGEN MINDRICELU P</creatorcontrib><creatorcontrib>HU BINGHUA</creatorcontrib><creatorcontrib>WOFFORD BILL A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GILMORE DAMIEN T</au><au>EUGEN MINDRICELU P</au><au>HU BINGHUA</au><au>WOFFORD BILL A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof</title><date>2010-01-07</date><risdate>2010</risdate><abstract>One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2010001364A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor Device Having Improved Oxide Thickness at a Shallow Trench Isolation Edge and Method of Manufacture Thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T14%3A57%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GILMORE%20DAMIEN%20T&rft.date=2010-01-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2010001364A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true