Method of construction of CTE matching structure with wafer processing and resulting structure

Method of construction of CTE matching structure with wafer processing and resulting structure

A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side o...

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Hauptverfasser: GERBER KENNETH A, GINN ROBERT P
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator GERBER KENNETH A
GINN ROBERT P
description A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010001188A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010001188A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010001188A13</originalsourceid><addsrcrecordid>eNqNirEKwjAQQLM4iPoPB85CoktXKRUXJ-tqCenFBtpcyF3o70vRxc3p8XhvrZ43lIF6IA-OIksuTgLFxeu2gcmKG0J8waeUjDAHGWC2HjOkTA6Zl25jDxm5jPJzb9XK25Fx9-VG7S9NW18PmKhDTtZhROke96M2WmtjqupsTv9db15UPgA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of construction of CTE matching structure with wafer processing and resulting structure</title><source>esp@cenet</source><creator>GERBER KENNETH A ; GINN ROBERT P</creator><creatorcontrib>GERBER KENNETH A ; GINN ROBERT P</creatorcontrib><description>A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100107&amp;DB=EPODOC&amp;CC=US&amp;NR=2010001188A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100107&amp;DB=EPODOC&amp;CC=US&amp;NR=2010001188A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GERBER KENNETH A</creatorcontrib><creatorcontrib>GINN ROBERT P</creatorcontrib><title>Method of construction of CTE matching structure with wafer processing and resulting structure</title><description>A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirEKwjAQQLM4iPoPB85CoktXKRUXJ-tqCenFBtpcyF3o70vRxc3p8XhvrZ43lIF6IA-OIksuTgLFxeu2gcmKG0J8waeUjDAHGWC2HjOkTA6Zl25jDxm5jPJzb9XK25Fx9-VG7S9NW18PmKhDTtZhROke96M2WmtjqupsTv9db15UPgA</recordid><startdate>20100107</startdate><enddate>20100107</enddate><creator>GERBER KENNETH A</creator><creator>GINN ROBERT P</creator><scope>EVB</scope></search><sort><creationdate>20100107</creationdate><title>Method of construction of CTE matching structure with wafer processing and resulting structure</title><author>GERBER KENNETH A ; GINN ROBERT P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010001188A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GERBER KENNETH A</creatorcontrib><creatorcontrib>GINN ROBERT P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GERBER KENNETH A</au><au>GINN ROBERT P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of construction of CTE matching structure with wafer processing and resulting structure</title><date>2010-01-07</date><risdate>2010</risdate><abstract>A method includes bonding a first side of a metal shim to a silicon shim, removing metal from the metal shim to form a plurality of cleared metal lanes in accordance with a pattern, bonding a readout integrated circuit having a plurality of saw lanes in accordance with the pattern to a second side of the metal shim to form a wafer assembly wherein the plurality of saw lanes is aligned with the plurality of cleared metal lanes, and dicing the wafer assembly.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of construction of CTE matching structure with wafer processing and resulting structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T21%3A28%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GERBER%20KENNETH%20A&rft.date=2010-01-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2010001188A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true