Design-For-Test-Aware Hierarchical Design Planning

Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. Th...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MATHEW BEN, LIU BANG, YEAP GARY K, CHIEN HUNGUN, TAI CHANG-WEI, TAKKARS PADMASHREE, XIONG XIAO-MING
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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