SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS

SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS

A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amoun...

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Hauptverfasser: TSUCHIYA KENICHI, GEROWITZ ROBERT GLEN
Format: Patent
Sprache:eng
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator TSUCHIYA KENICHI
GEROWITZ ROBERT GLEN
description A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.
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STATIC STORES
title SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS
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