ESD PROTECTION CIRCUIT AND METHOD
A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven device operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resisto...
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| creator | LIN SHU-HUEI WU YI-HSUN LIN YUANG GAN CHONG-GIM |
| description | A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven device operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor and a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge. |
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| subjects | BASIC ELECTRIC ELEMENTS CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS GENERATION SEMICONDUCTOR DEVICES |
| title | ESD PROTECTION CIRCUIT AND METHOD |
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