BUFFER INSERTION TO REDUCE WIRELENGTH IN VLSI CIRCUITS

Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MAHMUD TUHIN, ALPERT CHARLES J, QUAY STEPHEN T
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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