WAFER LEVEL PACKAGING OF SEMICONDUCTOR CHIPS

A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ZBRZEZNY ADAM, MCLELLAN NEIL
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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