Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby
A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the acti...
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creator | BAE SU-GON YOUN KI-SEOG AHN JONG-HYON |
description | A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2009051014A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2009051014A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2009051014A13</originalsourceid><addsrcrecordid>eNqNjL0KAjEQBq-xEPUdFqyFxJ_CUkSxsVLrYy_5zizE5Ejiwb29INpZWE0xw4wrf0Zx0VJsqeUmieEi4U4ZDzEx2KcpMZFFLwbkuH878WLEgjwPSMTB_s6_P1gqDgnNMK1GLfuM2YeTan48XPenBbpYI3dsEFDq22Wp1FZttNLrnV79V70AfhpDTA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby</title><source>esp@cenet</source><creator>BAE SU-GON ; YOUN KI-SEOG ; AHN JONG-HYON</creator><creatorcontrib>BAE SU-GON ; YOUN KI-SEOG ; AHN JONG-HYON</creatorcontrib><description>A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090226&DB=EPODOC&CC=US&NR=2009051014A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090226&DB=EPODOC&CC=US&NR=2009051014A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BAE SU-GON</creatorcontrib><creatorcontrib>YOUN KI-SEOG</creatorcontrib><creatorcontrib>AHN JONG-HYON</creatorcontrib><title>Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby</title><description>A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjL0KAjEQBq-xEPUdFqyFxJ_CUkSxsVLrYy_5zizE5Ejiwb29INpZWE0xw4wrf0Zx0VJsqeUmieEi4U4ZDzEx2KcpMZFFLwbkuH878WLEgjwPSMTB_s6_P1gqDgnNMK1GLfuM2YeTan48XPenBbpYI3dsEFDq22Wp1FZttNLrnV79V70AfhpDTA</recordid><startdate>20090226</startdate><enddate>20090226</enddate><creator>BAE SU-GON</creator><creator>YOUN KI-SEOG</creator><creator>AHN JONG-HYON</creator><scope>EVB</scope></search><sort><creationdate>20090226</creationdate><title>Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby</title><author>BAE SU-GON ; YOUN KI-SEOG ; AHN JONG-HYON</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2009051014A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BAE SU-GON</creatorcontrib><creatorcontrib>YOUN KI-SEOG</creatorcontrib><creatorcontrib>AHN JONG-HYON</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BAE SU-GON</au><au>YOUN KI-SEOG</au><au>AHN JONG-HYON</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby</title><date>2009-02-26</date><risdate>2009</risdate><abstract>A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby |
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