THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR

A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SNYDER MICHAEL D, BRUCE KLAS M, SMITTLE MATT B, WHISENHUNT GARY L, SCHULER SERGIO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SNYDER MICHAEL D
BRUCE KLAS M
SMITTLE MATT B
WHISENHUNT GARY L
SCHULER SERGIO
description A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2008282251A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2008282251A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2008282251A13</originalsourceid><addsrcrecordid>eNrjZLAK8QhydXRRcHHVdfUN8HAM9gxW8PQLDgkKdQ7x9PdTcPMPUvAN9QnxhKhzdVEICPJ3dg0O9g_iYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBgYWRhZGRqaGjobGxKkCAH7TKk4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR</title><source>esp@cenet</source><creator>SNYDER MICHAEL D ; BRUCE KLAS M ; SMITTLE MATT B ; WHISENHUNT GARY L ; SCHULER SERGIO</creator><creatorcontrib>SNYDER MICHAEL D ; BRUCE KLAS M ; SMITTLE MATT B ; WHISENHUNT GARY L ; SCHULER SERGIO</creatorcontrib><description>A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20081113&amp;DB=EPODOC&amp;CC=US&amp;NR=2008282251A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20081113&amp;DB=EPODOC&amp;CC=US&amp;NR=2008282251A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SNYDER MICHAEL D</creatorcontrib><creatorcontrib>BRUCE KLAS M</creatorcontrib><creatorcontrib>SMITTLE MATT B</creatorcontrib><creatorcontrib>WHISENHUNT GARY L</creatorcontrib><creatorcontrib>SCHULER SERGIO</creatorcontrib><title>THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR</title><description>A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAK8QhydXRRcHHVdfUN8HAM9gxW8PQLDgkKdQ7x9PdTcPMPUvAN9QnxhKhzdVEICPJ3dg0O9g_iYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBgYWRhZGRqaGjobGxKkCAH7TKk4</recordid><startdate>20081113</startdate><enddate>20081113</enddate><creator>SNYDER MICHAEL D</creator><creator>BRUCE KLAS M</creator><creator>SMITTLE MATT B</creator><creator>WHISENHUNT GARY L</creator><creator>SCHULER SERGIO</creator><scope>EVB</scope></search><sort><creationdate>20081113</creationdate><title>THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR</title><author>SNYDER MICHAEL D ; BRUCE KLAS M ; SMITTLE MATT B ; WHISENHUNT GARY L ; SCHULER SERGIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008282251A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SNYDER MICHAEL D</creatorcontrib><creatorcontrib>BRUCE KLAS M</creatorcontrib><creatorcontrib>SMITTLE MATT B</creatorcontrib><creatorcontrib>WHISENHUNT GARY L</creatorcontrib><creatorcontrib>SCHULER SERGIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SNYDER MICHAEL D</au><au>BRUCE KLAS M</au><au>SMITTLE MATT B</au><au>WHISENHUNT GARY L</au><au>SCHULER SERGIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR</title><date>2008-11-13</date><risdate>2008</risdate><abstract>A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2008282251A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T13%3A50%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SNYDER%20MICHAEL%20D&rft.date=2008-11-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2008282251A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true