SEMICONDUCTOR INTEGRATED CIRCUIT
A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing cha...
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| creator | MASUO AKIRA |
| description | A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2008211556A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2008211556A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2008211556A13</originalsourceid><addsrcrecordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBhZGhoampmaOhsbEqQIAmHQjEA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>MASUO AKIRA</creator><creatorcontrib>MASUO AKIRA</creatorcontrib><description>A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080904&DB=EPODOC&CC=US&NR=2008211556A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080904&DB=EPODOC&CC=US&NR=2008211556A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MASUO AKIRA</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><description>A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DOFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBhZGhoampmaOhsbEqQIAmHQjEA</recordid><startdate>20080904</startdate><enddate>20080904</enddate><creator>MASUO AKIRA</creator><scope>EVB</scope></search><sort><creationdate>20080904</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><author>MASUO AKIRA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008211556A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MASUO AKIRA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MASUO AKIRA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT</title><date>2008-09-04</date><risdate>2008</risdate><abstract>A delay clock circuit for delaying an input clock signal includes cascade connection of components each comprising first and second inverters. A delay clock control circuit is operated so that a through current can pass through a connection node between the first and second inverters for causing charge competition for a given period of time in transition of the input to the component. The delay clock control circuit includes a P-type transistor disposed, for example, between a power line and the connection node for receiving the output of the second inverter at the gate thereof.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES STATIC STORES |
| title | SEMICONDUCTOR INTEGRATED CIRCUIT |
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