METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE
During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processi...
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creator | RICHTER RALF SALZ HEIKE SCHALLER MATTHIAS |
description | During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing. Local removal of the second stressed layer may be performed on the basis of an etch time controlled etch process, which in some aspects may include the provision of an etch indicator material, wherein feed forward and feed back measurement data may be used in an appropriately designed process controller. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2008182346A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2008182346A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2008182346A13</originalsourceid><addsrcrecordid>eNqNjj0KAkEMhbexEPUOAWvBP8R2nMlqwE2WmaxgJSJjJSrouTyj2cUDWOUl70vy-sWnQt1JgFIiRAyNJ94Cqt9NiK3DAHUUjylBw2RQRUqYYHMEMaktHbCWZGNhkBIcA3KohVjNUfSdsXdHjBCa2C7UThUjt9IWkkY7b4_kgLHjEhCDg4QVeWlTqIULeCCPw6J3Pd9eefSrg2Jcdmnz83HKr-f5ku_5fWrSfDpdz9bzxXLlZov_qC_KVEov</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>RICHTER RALF ; SALZ HEIKE ; SCHALLER MATTHIAS</creator><creatorcontrib>RICHTER RALF ; SALZ HEIKE ; SCHALLER MATTHIAS</creatorcontrib><description>During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing. Local removal of the second stressed layer may be performed on the basis of an etch time controlled etch process, which in some aspects may include the provision of an etch indicator material, wherein feed forward and feed back measurement data may be used in an appropriately designed process controller.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080731&DB=EPODOC&CC=US&NR=2008182346A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080731&DB=EPODOC&CC=US&NR=2008182346A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RICHTER RALF</creatorcontrib><creatorcontrib>SALZ HEIKE</creatorcontrib><creatorcontrib>SCHALLER MATTHIAS</creatorcontrib><title>METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE</title><description>During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing. Local removal of the second stressed layer may be performed on the basis of an etch time controlled etch process, which in some aspects may include the provision of an etch indicator material, wherein feed forward and feed back measurement data may be used in an appropriately designed process controller.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjj0KAkEMhbexEPUOAWvBP8R2nMlqwE2WmaxgJSJjJSrouTyj2cUDWOUl70vy-sWnQt1JgFIiRAyNJ94Cqt9NiK3DAHUUjylBw2RQRUqYYHMEMaktHbCWZGNhkBIcA3KohVjNUfSdsXdHjBCa2C7UThUjt9IWkkY7b4_kgLHjEhCDg4QVeWlTqIULeCCPw6J3Pd9eefSrg2Jcdmnz83HKr-f5ku_5fWrSfDpdz9bzxXLlZov_qC_KVEov</recordid><startdate>20080731</startdate><enddate>20080731</enddate><creator>RICHTER RALF</creator><creator>SALZ HEIKE</creator><creator>SCHALLER MATTHIAS</creator><scope>EVB</scope></search><sort><creationdate>20080731</creationdate><title>METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE</title><author>RICHTER RALF ; SALZ HEIKE ; SCHALLER MATTHIAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008182346A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RICHTER RALF</creatorcontrib><creatorcontrib>SALZ HEIKE</creatorcontrib><creatorcontrib>SCHALLER MATTHIAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RICHTER RALF</au><au>SALZ HEIKE</au><au>SCHALLER MATTHIAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE</title><date>2008-07-31</date><risdate>2008</risdate><abstract>During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this layer during the subsequent processing. Local removal of the second stressed layer may be performed on the basis of an etch time controlled etch process, which in some aspects may include the provision of an etch indicator material, wherein feed forward and feed back measurement data may be used in an appropriately designed process controller.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE |
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