Tier-based memory read/write micro-command scheduler

Tier-based memory read/write micro-command scheduler

A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of ea...

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Hauptverfasser: BOGIN ZOHAR, KAREENAHALLI SURYA
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator BOGIN ZOHAR
KAREENAHALLI SURYA
description A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.
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In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080703&amp;DB=EPODOC&amp;CC=US&amp;NR=2008162852A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080703&amp;DB=EPODOC&amp;CC=US&amp;NR=2008162852A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BOGIN ZOHAR</creatorcontrib><creatorcontrib>KAREENAHALLI SURYA</creatorcontrib><title>Tier-based memory read/write micro-command scheduler</title><description>A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJyUwt0k1KLE5NUchNzc0vqlQoSk1M0S8vyixJVcjNTC7K103Oz81NzEtRKE7OSE0pzUkt4mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgYGFoZmRhamRo6GxsSpAgDi5i3H</recordid><startdate>20080703</startdate><enddate>20080703</enddate><creator>BOGIN ZOHAR</creator><creator>KAREENAHALLI SURYA</creator><scope>EVB</scope></search><sort><creationdate>20080703</creationdate><title>Tier-based memory read/write micro-command scheduler</title><author>BOGIN ZOHAR ; KAREENAHALLI SURYA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008162852A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>BOGIN ZOHAR</creatorcontrib><creatorcontrib>KAREENAHALLI SURYA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BOGIN ZOHAR</au><au>KAREENAHALLI SURYA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Tier-based memory read/write micro-command scheduler</title><date>2008-07-03</date><risdate>2008</risdate><abstract>A method, apparatus, and system are described. In one embodiment, the method comprises a chipset receiving a plurality of memory requests, wherein each memory request comprises one or more micro-commands that each require one or more memory clock cycles to execute, and scheduling the execution of each of the micro-commands from more than one of the plurality of memory requests in an order to reduce the number of total memory clock cycles required to complete execution of the more than one memory requests.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Tier-based memory read/write micro-command scheduler
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