Memory system with a configurable number of read data bits

In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes in the memory chips are to be used to carry read data in response to a read request and whether some of the interface lanes are used for carrying read data signals or command signals. Other embodiments are described.