Semiconductor Scheme for Reduced Circuit Area in a Simplified Process

Semiconductor Scheme for Reduced Circuit Area in a Simplified Process

An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilic...

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Hauptverfasser: DONZE RICHARD L, KUEPER TERRANCE W, HOVIS WILLIAM P, SHEETS JOHN E.II, CHRISTENSEN TODD A
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator DONZE RICHARD L
KUEPER TERRANCE W
HOVIS WILLIAM P
SHEETS JOHN E.II
CHRISTENSEN TODD A
description An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor Scheme for Reduced Circuit Area in a Simplified Process
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