Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory
Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WU MIN-TA LEE SHININ HSIEH JUNG-YU HSIEH KUANG Y LAI ERH-KUN SHIH YEN-HAO |
| description | Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3x10/cm-2, and methods for forming such memory cells. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2008096396A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2008096396A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2008096396A13</originalsourceid><addsrcrecordid>eNqNjcEKgkAURd20iOofHrQemBIklyGJi2yjtZVB34yCzhvejIR_n0Qf0Opw4VzONtIlhp46D6QhJ54Ga-BObyiWjsmghYxsizawCgOtq1dsUNSsnPuqakGGKvDchpnRgyaGB1nxonF9jAglTsTLPtpoNXo8_LiLjvmtzgqBjhr0Tq0NDM2zOkt5kWkSp8n1FP9nfQA76EBQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory</title><source>esp@cenet</source><creator>WU MIN-TA ; LEE SHININ ; HSIEH JUNG-YU ; HSIEH KUANG Y ; LAI ERH-KUN ; SHIH YEN-HAO</creator><creatorcontrib>WU MIN-TA ; LEE SHININ ; HSIEH JUNG-YU ; HSIEH KUANG Y ; LAI ERH-KUN ; SHIH YEN-HAO</creatorcontrib><description>Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3x10/cm-2, and methods for forming such memory cells.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080424&DB=EPODOC&CC=US&NR=2008096396A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080424&DB=EPODOC&CC=US&NR=2008096396A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WU MIN-TA</creatorcontrib><creatorcontrib>LEE SHININ</creatorcontrib><creatorcontrib>HSIEH JUNG-YU</creatorcontrib><creatorcontrib>HSIEH KUANG Y</creatorcontrib><creatorcontrib>LAI ERH-KUN</creatorcontrib><creatorcontrib>SHIH YEN-HAO</creatorcontrib><title>Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory</title><description>Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3x10/cm-2, and methods for forming such memory cells.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjcEKgkAURd20iOofHrQemBIklyGJi2yjtZVB34yCzhvejIR_n0Qf0Opw4VzONtIlhp46D6QhJ54Ga-BObyiWjsmghYxsizawCgOtq1dsUNSsnPuqakGGKvDchpnRgyaGB1nxonF9jAglTsTLPtpoNXo8_LiLjvmtzgqBjhr0Tq0NDM2zOkt5kWkSp8n1FP9nfQA76EBQ</recordid><startdate>20080424</startdate><enddate>20080424</enddate><creator>WU MIN-TA</creator><creator>LEE SHININ</creator><creator>HSIEH JUNG-YU</creator><creator>HSIEH KUANG Y</creator><creator>LAI ERH-KUN</creator><creator>SHIH YEN-HAO</creator><scope>EVB</scope></search><sort><creationdate>20080424</creationdate><title>Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory</title><author>WU MIN-TA ; LEE SHININ ; HSIEH JUNG-YU ; HSIEH KUANG Y ; LAI ERH-KUN ; SHIH YEN-HAO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2008096396A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WU MIN-TA</creatorcontrib><creatorcontrib>LEE SHININ</creatorcontrib><creatorcontrib>HSIEH JUNG-YU</creatorcontrib><creatorcontrib>HSIEH KUANG Y</creatorcontrib><creatorcontrib>LAI ERH-KUN</creatorcontrib><creatorcontrib>SHIH YEN-HAO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WU MIN-TA</au><au>LEE SHININ</au><au>HSIEH JUNG-YU</au><au>HSIEH KUANG Y</au><au>LAI ERH-KUN</au><au>SHIH YEN-HAO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory</title><date>2008-04-24</date><risdate>2008</risdate><abstract>Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3x10/cm-2, and methods for forming such memory cells.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2008096396A1 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Methods of Forming Low Hydrogen Concentration Charge-Trapping Layer Structures for Non-Volatile Memory |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T21%3A56%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WU%20MIN-TA&rft.date=2008-04-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2008096396A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |