Phase control circuit
A phase control circuit includes: a variable delay circuit for delaying a clock signal; a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input; a second flip-flop circuit having a clock input termin...
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creator | YAKIHARA TSUYOSHI TANIMURA DAISUKE TEZUKA KENTARO KODAKA HIROTOSHI UCHIDA KENJI MIURA AKIRA BUTATSU KENTARO |
description | A phase control circuit includes: a variable delay circuit for delaying a clock signal; a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input; a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and an integration circuit for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit. |
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a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input; a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and an integration circuit for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080103&DB=EPODOC&CC=US&NR=2008001641A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080103&DB=EPODOC&CC=US&NR=2008001641A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YAKIHARA TSUYOSHI</creatorcontrib><creatorcontrib>TANIMURA DAISUKE</creatorcontrib><creatorcontrib>TEZUKA KENTARO</creatorcontrib><creatorcontrib>KODAKA HIROTOSHI</creatorcontrib><creatorcontrib>UCHIDA KENJI</creatorcontrib><creatorcontrib>MIURA AKIRA</creatorcontrib><creatorcontrib>BUTATSU KENTARO</creatorcontrib><title>Phase control circuit</title><description>A phase control circuit includes: a variable delay circuit for delaying a clock signal; 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a first flip-flop circuit having a clock input terminal to which the delayed clock signal is input and a data input terminal to which a data signal is input; a second flip-flop circuit having a clock input terminal to which the data signal is input and a data input terminal to which the delayed clock signal is input; and an integration circuit for controlling a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit.</abstract><oa>free_for_read</oa></addata></record> |
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language | eng |
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subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | Phase control circuit |
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