STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS

STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS

Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ZIMMERMAN JEFFREY S, ENG CHUNG-PING, BONGES HENRY A, HOOK TERENCE B
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.