Printed Circuit Board and Manufacturing Method Thereof

A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulati...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: HONJO MITSURU
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HONJO MITSURU
description A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2007227764A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2007227764A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2007227764A13</originalsourceid><addsrcrecordid>eNrjZDALKMrMK0lNUXDOLEouzSxRcMpPLEpRSMxLUfBNzCtNS0wuKQWqSFfwTS3JyE9RCMlILUrNT-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBuZGRubmZiaOhsbEqQIAIvUuIQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Printed Circuit Board and Manufacturing Method Thereof</title><source>esp@cenet</source><creator>HONJO MITSURU</creator><creatorcontrib>HONJO MITSURU</creatorcontrib><description>A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20071004&amp;DB=EPODOC&amp;CC=US&amp;NR=2007227764A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20071004&amp;DB=EPODOC&amp;CC=US&amp;NR=2007227764A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HONJO MITSURU</creatorcontrib><title>Printed Circuit Board and Manufacturing Method Thereof</title><description>A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALKMrMK0lNUXDOLEouzSxRcMpPLEpRSMxLUfBNzCtNS0wuKQWqSFfwTS3JyE9RCMlILUrNT-NhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBuZGRubmZiaOhsbEqQIAIvUuIQ</recordid><startdate>20071004</startdate><enddate>20071004</enddate><creator>HONJO MITSURU</creator><scope>EVB</scope></search><sort><creationdate>20071004</creationdate><title>Printed Circuit Board and Manufacturing Method Thereof</title><author>HONJO MITSURU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2007227764A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>HONJO MITSURU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HONJO MITSURU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Printed Circuit Board and Manufacturing Method Thereof</title><date>2007-10-04</date><risdate>2007</risdate><abstract>A plurality of wiring patterns in a stripe form are formed to be parallel to one another on one surface of a base insulating layer. The wiring patterns each have a layered structure including a conductive layer and a wiring layer. A thin metal film is formed on the other surface of the base insulating layer, and a plurality of ground patterns in a stripe form are formed to be parallel to one another on the thin metal film. The wiring patterns and the ground patterns are provided in a staggered manner so that they are not opposed to one another with the base insulating layer interposed therebetween. In other words, the ground patterns are provided to be opposed to regions between the wiring patterns.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2007227764A1
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title Printed Circuit Board and Manufacturing Method Thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T22%3A29%3A01IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HONJO%20MITSURU&rft.date=2007-10-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2007227764A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true