Fully-depleted castellated gate MOSFET device and method of manufacture thereof

A fully depleted castellated-gate MOSFET device is disclosed along with a method of making the same. The device has robust I/O applications, and includes a semiconductor substrate body having an upper portion with an upper end surface and a lower portion with a lower end surface. A source region, a...

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Bibliographische Detailangaben
1. Verfasser: SELISKAR JOHN J
Format: Patent
Sprache:eng
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