Program method and circuit of non-volatile memory
A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled t...
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creator | YEH CHIHIEH |
description | A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage. |
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The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070322&DB=EPODOC&CC=US&NR=2007064487A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070322&DB=EPODOC&CC=US&NR=2007064487A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YEH CHIHIEH</creatorcontrib><title>Program method and circuit of non-volatile memory</title><description>A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAMKMpPL0rMVchNLcnIT1FIzEtRSM4sSi7NLFHIT1PIy8_TLcvPSSzJzEkFKsnNL6rkYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBgbmBmYmJhbmjobGxKkCADvZLJ0</recordid><startdate>20070322</startdate><enddate>20070322</enddate><creator>YEH CHIHIEH</creator><scope>EVB</scope></search><sort><creationdate>20070322</creationdate><title>Program method and circuit of non-volatile memory</title><author>YEH CHIHIEH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2007064487A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>YEH CHIHIEH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YEH CHIHIEH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Program method and circuit of non-volatile memory</title><date>2007-03-22</date><risdate>2007</risdate><abstract>A circuit of non-volatile memory which includes a plurality of memory units is disclosed. The memory unit comprises a first switch, a second switch, a data line, a voltage storage component, and a plurality of memory components connected in series. The first terminal of the first switch is coupled to the first voltage. The data line is coupled to the second terminal of the first switch. The first terminal of the voltage storage component is coupled to the data line, and the second terminal of the voltage storage component is coupled to the ground. The first terminal of the second switch is coupled the data line. In addition, the third terminal of each memory component is coupled to the first terminal of the next memory component, and the second terminal of the each memory component is coupled to second voltage.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Program method and circuit of non-volatile memory |
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