Area efficient BIST system for memories

A system with a single BIST for an IC that includes a number of memory arrays that may have varying latencies, widths, and depths. A serial bus (which may be a debug bus) connects the BIST controller, each of the memory arrays on the IC, and a controller. Each memory array has an associated Design f...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	THUSOO SHALESH, NJINDA CHARLES A, WANG HAO
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS STATIC STORES TESTING
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