Method of fabricating flash memory device

The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of integration...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SHIN HYEON S
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHIN HYEON S
description The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of integration of a device can be improved. A channel is formed not only an active region but also sidewalls of trenches at both sides of the active region, thus extending an effective channel length. It is thus possible to compensate for a reduction in the cell current depending upon a reduction of the width of the active region (line).
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2006205152A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2006205152A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2006205152A13</originalsourceid><addsrcrecordid>eNrjZND0TS3JyE9RyE9TSEtMKspMTizJzEtXSMtJLM5QyE3NzS-qVEhJLctMTuVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBmZGBqaGpkaOhsbEqQIAiaUpWQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of fabricating flash memory device</title><source>esp@cenet</source><creator>SHIN HYEON S</creator><creatorcontrib>SHIN HYEON S</creatorcontrib><description>The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of integration of a device can be improved. A channel is formed not only an active region but also sidewalls of trenches at both sides of the active region, thus extending an effective channel length. It is thus possible to compensate for a reduction in the cell current depending upon a reduction of the width of the active region (line).</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060914&amp;DB=EPODOC&amp;CC=US&amp;NR=2006205152A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20060914&amp;DB=EPODOC&amp;CC=US&amp;NR=2006205152A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIN HYEON S</creatorcontrib><title>Method of fabricating flash memory device</title><description>The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of integration of a device can be improved. A channel is formed not only an active region but also sidewalls of trenches at both sides of the active region, thus extending an effective channel length. It is thus possible to compensate for a reduction in the cell current depending upon a reduction of the width of the active region (line).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND0TS3JyE9RyE9TSEtMKspMTizJzEtXSMtJLM5QyE3NzS-qVEhJLctMTuVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBmZGBqaGpkaOhsbEqQIAiaUpWQ</recordid><startdate>20060914</startdate><enddate>20060914</enddate><creator>SHIN HYEON S</creator><scope>EVB</scope></search><sort><creationdate>20060914</creationdate><title>Method of fabricating flash memory device</title><author>SHIN HYEON S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2006205152A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIN HYEON S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIN HYEON S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of fabricating flash memory device</title><date>2006-09-14</date><risdate>2006</risdate><abstract>The present invention relates to a method of fabricating a flash memory device. The width of an active region (line) is reduced, but the width of a field region (space) is extended. An overlay margin between the floating gates and the active region depending upon increase in the level of integration of a device can be improved. A channel is formed not only an active region but also sidewalls of trenches at both sides of the active region, thus extending an effective channel length. It is thus possible to compensate for a reduction in the cell current depending upon a reduction of the width of the active region (line).</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2006205152A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method of fabricating flash memory device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T12%3A26%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHIN%20HYEON%20S&rft.date=2006-09-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2006205152A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true