High performance chip scale leadframe with t-shape die pad and method of manufacturing package
An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is...
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| creator | POH FRANCIS KOON S TAN HIEN B SUN ANTHONY Y.S |
| description | An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined. |
| format | Patent |
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The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060914&DB=EPODOC&CC=US&NR=2006202313A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060914&DB=EPODOC&CC=US&NR=2006202313A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>POH FRANCIS KOON S</creatorcontrib><creatorcontrib>TAN HIEN B</creatorcontrib><creatorcontrib>SUN ANTHONY Y.S</creatorcontrib><title>High performance chip scale leadframe with t-shape die pad and method of manufacturing package</title><description>An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7sKAjEUBdNYiPoPF6wX9gH2Isr2autySU4euHmQZPH33cIPsJpiZrbiNTpjKSHrmD0HCZLWJSqSZ9AMVjqzB31ctVSbYjmBlAMlVsRBkUe1UVHUtN6LZlmX7IJZvXyzwV5sNM8Fhx934ni7Pi5jgxQnlLVCQJ2e975tT33bD91w7ob_qi_HJDy8</recordid><startdate>20060914</startdate><enddate>20060914</enddate><creator>POH FRANCIS KOON S</creator><creator>TAN HIEN B</creator><creator>SUN ANTHONY Y.S</creator><scope>EVB</scope></search><sort><creationdate>20060914</creationdate><title>High performance chip scale leadframe with t-shape die pad and method of manufacturing package</title><author>POH FRANCIS KOON S ; TAN HIEN B ; SUN ANTHONY Y.S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2006202313A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>POH FRANCIS KOON S</creatorcontrib><creatorcontrib>TAN HIEN B</creatorcontrib><creatorcontrib>SUN ANTHONY Y.S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>POH FRANCIS KOON S</au><au>TAN HIEN B</au><au>SUN ANTHONY Y.S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>High performance chip scale leadframe with t-shape die pad and method of manufacturing package</title><date>2006-09-14</date><risdate>2006</risdate><abstract>An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | High performance chip scale leadframe with t-shape die pad and method of manufacturing package |
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