Selective formation of metal layers in an integrated circuit

A method for enhancing the reliability of copper interconnects and/or contacts, such as the bottom of vias exposing top surfaces of buried copper, or at the top of copper lines just after CMP. The method comprises contacting the exposed copper surface with a vapor phase compound of a noble metal and...

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Hauptverfasser:	TUOMINEN MARKO, LEINIKKA MIIKA, HUOTARI HANNU A, KOH WONYONG, KILPELA OLLI V
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	TUOMINEN MARKO LEINIKKA MIIKA HUOTARI HANNU A KOH WONYONG KILPELA OLLI V
description	A method for enhancing the reliability of copper interconnects and/or contacts, such as the bottom of vias exposing top surfaces of buried copper, or at the top of copper lines just after CMP. The method comprises contacting the exposed copper surface with a vapor phase compound of a noble metal and selectively forming a layer of the noble metal on the exposed copper surface, either by a copper replacement reaction or selective deposition (e.g., ALD or CVD) of the noble metal.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Selective formation of metal layers in an integrated circuit
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