Method of making a circuitized substrate having a plurality of solder connection sites thereon
A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of d...
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creator | RIOS JOSE A KONRAD JOHN J KOTYLO JOSEPH A |
description | A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described. |
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In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060511&DB=EPODOC&CC=US&NR=2006099727A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20060511&DB=EPODOC&CC=US&NR=2006099727A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RIOS JOSE A</creatorcontrib><creatorcontrib>KONRAD JOHN J</creatorcontrib><creatorcontrib>KOTYLO JOSEPH A</creatorcontrib><title>Method of making a circuitized substrate having a plurality of solder connection sites thereon</title><description>A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. 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An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizEKwkAQANNYiPqHBWshRjCkFFFsrNTWsF423uJ5G243gr5eRB9gNcXMDLPznsxLA9LCHW8cr4DgOLmejV_UgPYXtYRG4PHx1V3oEwa252dSCQ0lcBIjOWOJoGykYJ4SSRxngxaD0uTHUTbdbo7r3Yw6qUk7dBTJ6tOhyPNlXlVlUa7mi_-qN0aePeY</recordid><startdate>20060511</startdate><enddate>20060511</enddate><creator>RIOS JOSE A</creator><creator>KONRAD JOHN J</creator><creator>KOTYLO JOSEPH A</creator><scope>EVB</scope></search><sort><creationdate>20060511</creationdate><title>Method of making a circuitized substrate having a plurality of solder connection sites thereon</title><author>RIOS JOSE A ; KONRAD JOHN J ; KOTYLO JOSEPH A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2006099727A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RIOS JOSE A</creatorcontrib><creatorcontrib>KONRAD JOHN J</creatorcontrib><creatorcontrib>KOTYLO JOSEPH A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RIOS JOSE A</au><au>KONRAD JOHN J</au><au>KOTYLO JOSEPH A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of making a circuitized substrate having a plurality of solder connection sites thereon</title><date>2006-05-11</date><risdate>2006</risdate><abstract>A method of making a circuitized substrate in which two solder deposits, either of the same or different metallurgies, are formed on at least two different metal or metal alloy conductors and PTHs. In an alternative embodiment, the same solder compositions may be deposited on conductor and PTHs of different metal or metal alloy composition. In each embodiment, a single commoning layer (e.g., copper) is used, being partially removed following the first deposition. The solder is deposited using an electroplating process (electroless or electrolytic) and the commoning bar in both depositing steps. An information handling system utilizing the circuitized substrate formed in accordance with the invention is also described.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | Method of making a circuitized substrate having a plurality of solder connection sites thereon |
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