Information processing electronic device

Provided is an information processing electronic device by which even if a CPU and/or information processing integrated circuit enters a sleep mode in a frequency of 100 to 10,000 times per second, a leakage current loss caused in the CPU or integrated circuit in a transition time of rise and fall of a supply voltage is reduced, a loss reduction effect in such highly frequent sleep function is maximized and a smaller and lighter device is realized. While at least one of the CPU and information processing integrated circuit is frequently applied with a sleep control, a DC/DC converter which includes at least one SiGe bipolar transistor for switching operation, supplying the CPU and/or information processing integrated circuit with the power has a capacity to put out a power of 20 to 50 W as well as has at least one inductor of the DC/DC converter, the at least one inductor being so constructed that an equivalent inductance value thereof is 0.04 to 0.75 uH; when the DC/DC converter has a capacity to put out a power of 20 W, the at least one inductor is so constructed that the equivalent inductance value thereof is 0.15 to 0.75 pH; and when the DC/DC converter has a capacity to put out a power of 50 W, the at least one inductor is so constructed that the equivalent inductance value thereof is 0.04 to 0.2 pH.