Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown

A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transi...

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Hauptverfasser: PENG JACK Z, YE FEI, FLIESLER MICHAEL D, LIU ZHONGSHAN
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creator PENG JACK Z
YE FEI
FLIESLER MICHAEL D
LIU ZHONGSHAN
description A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2005169039A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2005169039A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2005169039A13</originalsourceid><addsrcrecordid>eNqNzbEKwkAQBNA0FqL-w4J1IDEopJSg2Kt12OTWsHjZDXenMX_i5xpQEKyspnkzM42ehbYVCwZWgQuTNdA5bRy2LVaWoMFAgM7hAGit9iwNmEGw5RocfSlbDiMRA6IS39WOi2P9F1ToycCtG8-CQ_Hsg7r3iT7YEFSO8Gq0l3k0uaD1tPjkLFrud6fiEFOnJfkOaxIK5fm4SpJ1usmTLN-m2X_qBcHXVQQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown</title><source>esp@cenet</source><creator>PENG JACK Z ; YE FEI ; FLIESLER MICHAEL D ; LIU ZHONGSHAN</creator><creatorcontrib>PENG JACK Z ; YE FEI ; FLIESLER MICHAEL D ; LIU ZHONGSHAN</creatorcontrib><description>A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20050804&amp;DB=EPODOC&amp;CC=US&amp;NR=2005169039A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20050804&amp;DB=EPODOC&amp;CC=US&amp;NR=2005169039A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PENG JACK Z</creatorcontrib><creatorcontrib>YE FEI</creatorcontrib><creatorcontrib>FLIESLER MICHAEL D</creatorcontrib><creatorcontrib>LIU ZHONGSHAN</creatorcontrib><title>Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown</title><description>A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzbEKwkAQBNA0FqL-w4J1IDEopJSg2Kt12OTWsHjZDXenMX_i5xpQEKyspnkzM42ehbYVCwZWgQuTNdA5bRy2LVaWoMFAgM7hAGit9iwNmEGw5RocfSlbDiMRA6IS39WOi2P9F1ToycCtG8-CQ_Hsg7r3iT7YEFSO8Gq0l3k0uaD1tPjkLFrud6fiEFOnJfkOaxIK5fm4SpJ1usmTLN-m2X_qBcHXVQQ</recordid><startdate>20050804</startdate><enddate>20050804</enddate><creator>PENG JACK Z</creator><creator>YE FEI</creator><creator>FLIESLER MICHAEL D</creator><creator>LIU ZHONGSHAN</creator><scope>EVB</scope></search><sort><creationdate>20050804</creationdate><title>Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown</title><author>PENG JACK Z ; YE FEI ; FLIESLER MICHAEL D ; LIU ZHONGSHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2005169039A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>PENG JACK Z</creatorcontrib><creatorcontrib>YE FEI</creatorcontrib><creatorcontrib>FLIESLER MICHAEL D</creatorcontrib><creatorcontrib>LIU ZHONGSHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PENG JACK Z</au><au>YE FEI</au><au>FLIESLER MICHAEL D</au><au>LIU ZHONGSHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown</title><date>2005-08-04</date><risdate>2005</risdate><abstract>A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
STATIC STORES
title Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T19%3A21%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PENG%20JACK%20Z&rft.date=2005-08-04&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2005169039A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true