Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D...

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Bibliographische Detailangaben

Hauptverfasser:	GUARINI KATHRYN W, IEONG MEIKEI, CHAN VICTOR
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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