Regenerative clock repeater
A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. Thes...
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| creator | FRULIO MASSIMILIANO SIVERO STEFANO |
| description | A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal. |
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The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20041223&DB=EPODOC&CC=US&NR=2004257131A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20041223&DB=EPODOC&CC=US&NR=2004257131A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FRULIO MASSIMILIANO</creatorcontrib><creatorcontrib>SIVERO STEFANO</creatorcontrib><title>Regenerative clock repeater</title><description>A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOSk1PzUstSizJLEtVSM7JT85WKEotSE0sSS3iYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyUCdJfGhwUYGBiZGpuaGxoaOhsbEqQIAErMkbQ</recordid><startdate>20041223</startdate><enddate>20041223</enddate><creator>FRULIO MASSIMILIANO</creator><creator>SIVERO STEFANO</creator><scope>EVB</scope></search><sort><creationdate>20041223</creationdate><title>Regenerative clock repeater</title><author>FRULIO MASSIMILIANO ; SIVERO STEFANO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004257131A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FRULIO MASSIMILIANO</creatorcontrib><creatorcontrib>SIVERO STEFANO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FRULIO MASSIMILIANO</au><au>SIVERO STEFANO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Regenerative clock repeater</title><date>2004-12-23</date><risdate>2004</risdate><abstract>A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
| title | Regenerative clock repeater |
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