Electroplated interconnection structures on integrated circuit chips

A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal....

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Hauptverfasser: HORKANS WILMA JEAN, HU CHAO-KUN, HURD JEFFREY LOUIS, ANDRICACOS PANAYOTIS CONSTANTINOU, DELIGIANNI HARIKLIA, RODBELL KENNETH PARKER, DUKOVIC JOHN OWEN, WONG KWONG-HON, EDELSTEIN DANIEL CHARLES, UZOH CYPRIAN EMEKA
Format: Patent
Sprache:eng
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