SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating lay...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: LIN FENGUAN, CHEN YI-NAN, WU TIEHIANG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator LIN FENGUAN
CHEN YI-NAN
WU TIEHIANG
description A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004209422A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004209422A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004209422A13</originalsourceid><addsrcrecordid>eNqNi7EKwjAUALM4iPoPD5yFGLs4PpJXE2gSaV4DnUqROIkW6v9jET_A4bjlbi1yIu90DKbTHFswlJ0msJhduAC3FLQFjldwKTbILgZosKcWMBjwxDYaqJdvwX8PS5DQ01as7uNjLrufN2JfE2t7KNNrKPM03sqzvIcuKSkrJc-VUng8_Vd9AEliMWk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME</title><source>esp@cenet</source><creator>LIN FENGUAN ; CHEN YI-NAN ; WU TIEHIANG</creator><creatorcontrib>LIN FENGUAN ; CHEN YI-NAN ; WU TIEHIANG</creatorcontrib><description>A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041021&amp;DB=EPODOC&amp;CC=US&amp;NR=2004209422A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20041021&amp;DB=EPODOC&amp;CC=US&amp;NR=2004209422A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN FENGUAN</creatorcontrib><creatorcontrib>CHEN YI-NAN</creatorcontrib><creatorcontrib>WU TIEHIANG</creatorcontrib><title>SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME</title><description>A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwjAUALM4iPoPD5yFGLs4PpJXE2gSaV4DnUqROIkW6v9jET_A4bjlbi1yIu90DKbTHFswlJ0msJhduAC3FLQFjldwKTbILgZosKcWMBjwxDYaqJdvwX8PS5DQ01as7uNjLrufN2JfE2t7KNNrKPM03sqzvIcuKSkrJc-VUng8_Vd9AEliMWk</recordid><startdate>20041021</startdate><enddate>20041021</enddate><creator>LIN FENGUAN</creator><creator>CHEN YI-NAN</creator><creator>WU TIEHIANG</creator><scope>EVB</scope></search><sort><creationdate>20041021</creationdate><title>SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME</title><author>LIN FENGUAN ; CHEN YI-NAN ; WU TIEHIANG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004209422A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LIN FENGUAN</creatorcontrib><creatorcontrib>CHEN YI-NAN</creatorcontrib><creatorcontrib>WU TIEHIANG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LIN FENGUAN</au><au>CHEN YI-NAN</au><au>WU TIEHIANG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME</title><date>2004-10-21</date><risdate>2004</risdate><abstract>A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2004209422A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE HAVING TRENCH TOP ISOLATION LAYER AND METHOD FOR FORMING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T10%3A38%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LIN%20FENGUAN&rft.date=2004-10-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2004209422A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true