Electronic structures with reduced capacitance
An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the le...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Schreiben Sie den ersten Kommentar!