Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency

In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the...

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Hauptverfasser: MURATA YOSHITAKA, KAWASUMI YOKO, KUWANO AKIRA
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creator MURATA YOSHITAKA
KAWASUMI YOKO
KUWANO AKIRA
description In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and activates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004164811A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004164811A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004164811A13</originalsourceid><addsrcrecordid>eNqNjcFKxEAQRHPxIOo_NHgWN7qI12VRvKt4XNpOZdM46RmnJ0j8RX_KjIpePRUU9eodNh9P2oFClBfKbHtQGti_C3RLxERlTqA-43WCyUw-Wxng-o5MwomfAyj2BBvYRG1PKUPUNVqtv-7O_2iJY-LMJWZ60zLEqZCaZLBXtGqnxagjiK0jLU4jlllH_UI4AqTUYXTRELhUy-_5cXPQc3Cc_ORRc3p787C9O0OKO3higaHsHu8vVqt1e7W-bttNe_m_1SflW2fX</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency</title><source>esp@cenet</source><creator>MURATA YOSHITAKA ; KAWASUMI YOKO ; KUWANO AKIRA</creator><creatorcontrib>MURATA YOSHITAKA ; KAWASUMI YOKO ; KUWANO AKIRA</creatorcontrib><description>In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and activates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.</description><edition>7</edition><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040826&amp;DB=EPODOC&amp;CC=US&amp;NR=2004164811A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040826&amp;DB=EPODOC&amp;CC=US&amp;NR=2004164811A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MURATA YOSHITAKA</creatorcontrib><creatorcontrib>KAWASUMI YOKO</creatorcontrib><creatorcontrib>KUWANO AKIRA</creatorcontrib><title>Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency</title><description>In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and activates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjcFKxEAQRHPxIOo_NHgWN7qI12VRvKt4XNpOZdM46RmnJ0j8RX_KjIpePRUU9eodNh9P2oFClBfKbHtQGti_C3RLxERlTqA-43WCyUw-Wxng-o5MwomfAyj2BBvYRG1PKUPUNVqtv-7O_2iJY-LMJWZ60zLEqZCaZLBXtGqnxagjiK0jLU4jlllH_UI4AqTUYXTRELhUy-_5cXPQc3Cc_ORRc3p787C9O0OKO3higaHsHu8vVqt1e7W-bttNe_m_1SflW2fX</recordid><startdate>20040826</startdate><enddate>20040826</enddate><creator>MURATA YOSHITAKA</creator><creator>KAWASUMI YOKO</creator><creator>KUWANO AKIRA</creator><scope>EVB</scope></search><sort><creationdate>20040826</creationdate><title>Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency</title><author>MURATA YOSHITAKA ; KAWASUMI YOKO ; KUWANO AKIRA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004164811A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>MURATA YOSHITAKA</creatorcontrib><creatorcontrib>KAWASUMI YOKO</creatorcontrib><creatorcontrib>KUWANO AKIRA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MURATA YOSHITAKA</au><au>KAWASUMI YOKO</au><au>KUWANO AKIRA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency</title><date>2004-08-26</date><risdate>2004</risdate><abstract>In a phase locked loop type frequency synthesizer including a phase/frequency comparator for receiving an input signal, a charge pump circuit, a loop filter for generating a control voltage, a voltage control oscillator block including a plurality of voltage controlled oscillators controlled by the control voltage, and a frequency divider formed by a fixed frequency divider and a programmable frequency divider, a selecting circuit selects and activates only one of the voltage controlled oscillators, and counts a number of output pulses of the first frequency divider within a predetermined number of output pulses of the input signal while applying a bias voltage to the loop filter. Thus, the one of the voltage controlled oscillators being selected so that the number of the output pulses of the first frequency divider is brought close to an optimum value.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
title Wide lock range phase locked loop type frequency synthesizer capable of enhancing precision of phase/frequency comparator without increasing lockup time and its method for selecting oscillation frequency
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T06%3A53%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MURATA%20YOSHITAKA&rft.date=2004-08-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2004164811A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true