Method and circuit arrangement for memory error processing

The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the fa...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CUPPENS ROGER, SALTERS ROELOF, DITEWIG ANTHONIE MEINDERT HERMAN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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