Semiconductor integrated circuit
A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second...
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| creator | OGURA ISAO UEDA YOSHITAKA |
| description | A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits. |
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The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040805&DB=EPODOC&CC=US&NR=2004150442A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040805&DB=EPODOC&CC=US&NR=2004150442A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OGURA ISAO</creatorcontrib><creatorcontrib>UEDA YOSHITAKA</creatorcontrib><title>Semiconductor integrated circuit</title><description>A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAITs3NTM7PSylNLskvUsjMK0lNL0osSU1RSM4sSi7NLOFhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGBiaGpgYmJkaOhsbEqQIAHxwmoA</recordid><startdate>20040805</startdate><enddate>20040805</enddate><creator>OGURA ISAO</creator><creator>UEDA YOSHITAKA</creator><scope>EVB</scope></search><sort><creationdate>20040805</creationdate><title>Semiconductor integrated circuit</title><author>OGURA ISAO ; UEDA YOSHITAKA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004150442A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OGURA ISAO</creatorcontrib><creatorcontrib>UEDA YOSHITAKA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OGURA ISAO</au><au>UEDA YOSHITAKA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor integrated circuit</title><date>2004-08-05</date><risdate>2004</risdate><abstract>A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS BASIC ELECTRONIC CIRCUITRY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PULSE TECHNIQUE SEMICONDUCTOR DEVICES |
| title | Semiconductor integrated circuit |
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