Copper recess process with application to selective capping and electroless plating
An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the condu...
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| creator | KUMAR KAUSHIK MALHOTRA SANDRA G SIMON ANDREW H KRISHNAN MAHADEVAIYER SMITH SEAN P.E KALDOR STEFFEN K DALTON TIMOTHY J DAVIS KENNETH M HU CHAO-KUN RATH DAVID L TSENG WEI-TSU CHEN SHYNG-TSONG RUBINO JUDITH M NARAYAN CHANDRASEKHAR SAENGER KATHERINE L JAMIN FEN F LOFARO MICHAEL F |
| description | An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004113279A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004113279A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004113279A13</originalsourceid><addsrcrecordid>eNqNi0EKwjAQRbNxIeodBlwLTSuISymK--q6hPFbAyEzJEGvbwkewNWD999fmqEXVSRKYORMmqTy48uLnGrw7IqXSEUoI4CLf4N4XnycyMUHVZkk1HeY4zitzeLpQsbmx5XZXs63_rqDyoisjhFRxvvQNs3e2q49HE-2-6_6AoafOfU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Copper recess process with application to selective capping and electroless plating</title><source>esp@cenet</source><creator>KUMAR KAUSHIK ; MALHOTRA SANDRA G ; SIMON ANDREW H ; KRISHNAN MAHADEVAIYER ; SMITH SEAN P.E ; KALDOR STEFFEN K ; DALTON TIMOTHY J ; DAVIS KENNETH M ; HU CHAO-KUN ; RATH DAVID L ; TSENG WEI-TSU ; CHEN SHYNG-TSONG ; RUBINO JUDITH M ; NARAYAN CHANDRASEKHAR ; SAENGER KATHERINE L ; JAMIN FEN F ; LOFARO MICHAEL F</creator><creatorcontrib>KUMAR KAUSHIK ; MALHOTRA SANDRA G ; SIMON ANDREW H ; KRISHNAN MAHADEVAIYER ; SMITH SEAN P.E ; KALDOR STEFFEN K ; DALTON TIMOTHY J ; DAVIS KENNETH M ; HU CHAO-KUN ; RATH DAVID L ; TSENG WEI-TSU ; CHEN SHYNG-TSONG ; RUBINO JUDITH M ; NARAYAN CHANDRASEKHAR ; SAENGER KATHERINE L ; JAMIN FEN F ; LOFARO MICHAEL F</creatorcontrib><description>An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040617&DB=EPODOC&CC=US&NR=2004113279A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040617&DB=EPODOC&CC=US&NR=2004113279A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUMAR KAUSHIK</creatorcontrib><creatorcontrib>MALHOTRA SANDRA G</creatorcontrib><creatorcontrib>SIMON ANDREW H</creatorcontrib><creatorcontrib>KRISHNAN MAHADEVAIYER</creatorcontrib><creatorcontrib>SMITH SEAN P.E</creatorcontrib><creatorcontrib>KALDOR STEFFEN K</creatorcontrib><creatorcontrib>DALTON TIMOTHY J</creatorcontrib><creatorcontrib>DAVIS KENNETH M</creatorcontrib><creatorcontrib>HU CHAO-KUN</creatorcontrib><creatorcontrib>RATH DAVID L</creatorcontrib><creatorcontrib>TSENG WEI-TSU</creatorcontrib><creatorcontrib>CHEN SHYNG-TSONG</creatorcontrib><creatorcontrib>RUBINO JUDITH M</creatorcontrib><creatorcontrib>NARAYAN CHANDRASEKHAR</creatorcontrib><creatorcontrib>SAENGER KATHERINE L</creatorcontrib><creatorcontrib>JAMIN FEN F</creatorcontrib><creatorcontrib>LOFARO MICHAEL F</creatorcontrib><title>Copper recess process with application to selective capping and electroless plating</title><description>An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi0EKwjAQRbNxIeodBlwLTSuISymK--q6hPFbAyEzJEGvbwkewNWD999fmqEXVSRKYORMmqTy48uLnGrw7IqXSEUoI4CLf4N4XnycyMUHVZkk1HeY4zitzeLpQsbmx5XZXs63_rqDyoisjhFRxvvQNs3e2q49HE-2-6_6AoafOfU</recordid><startdate>20040617</startdate><enddate>20040617</enddate><creator>KUMAR KAUSHIK</creator><creator>MALHOTRA SANDRA G</creator><creator>SIMON ANDREW H</creator><creator>KRISHNAN MAHADEVAIYER</creator><creator>SMITH SEAN P.E</creator><creator>KALDOR STEFFEN K</creator><creator>DALTON TIMOTHY J</creator><creator>DAVIS KENNETH M</creator><creator>HU CHAO-KUN</creator><creator>RATH DAVID L</creator><creator>TSENG WEI-TSU</creator><creator>CHEN SHYNG-TSONG</creator><creator>RUBINO JUDITH M</creator><creator>NARAYAN CHANDRASEKHAR</creator><creator>SAENGER KATHERINE L</creator><creator>JAMIN FEN F</creator><creator>LOFARO MICHAEL F</creator><scope>EVB</scope></search><sort><creationdate>20040617</creationdate><title>Copper recess process with application to selective capping and electroless plating</title><author>KUMAR KAUSHIK ; MALHOTRA SANDRA G ; SIMON ANDREW H ; KRISHNAN MAHADEVAIYER ; SMITH SEAN P.E ; KALDOR STEFFEN K ; DALTON TIMOTHY J ; DAVIS KENNETH M ; HU CHAO-KUN ; RATH DAVID L ; TSENG WEI-TSU ; CHEN SHYNG-TSONG ; RUBINO JUDITH M ; NARAYAN CHANDRASEKHAR ; SAENGER KATHERINE L ; JAMIN FEN F ; LOFARO MICHAEL F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004113279A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>KUMAR KAUSHIK</creatorcontrib><creatorcontrib>MALHOTRA SANDRA G</creatorcontrib><creatorcontrib>SIMON ANDREW H</creatorcontrib><creatorcontrib>KRISHNAN MAHADEVAIYER</creatorcontrib><creatorcontrib>SMITH SEAN P.E</creatorcontrib><creatorcontrib>KALDOR STEFFEN K</creatorcontrib><creatorcontrib>DALTON TIMOTHY J</creatorcontrib><creatorcontrib>DAVIS KENNETH M</creatorcontrib><creatorcontrib>HU CHAO-KUN</creatorcontrib><creatorcontrib>RATH DAVID L</creatorcontrib><creatorcontrib>TSENG WEI-TSU</creatorcontrib><creatorcontrib>CHEN SHYNG-TSONG</creatorcontrib><creatorcontrib>RUBINO JUDITH M</creatorcontrib><creatorcontrib>NARAYAN CHANDRASEKHAR</creatorcontrib><creatorcontrib>SAENGER KATHERINE L</creatorcontrib><creatorcontrib>JAMIN FEN F</creatorcontrib><creatorcontrib>LOFARO MICHAEL F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUMAR KAUSHIK</au><au>MALHOTRA SANDRA G</au><au>SIMON ANDREW H</au><au>KRISHNAN MAHADEVAIYER</au><au>SMITH SEAN P.E</au><au>KALDOR STEFFEN K</au><au>DALTON TIMOTHY J</au><au>DAVIS KENNETH M</au><au>HU CHAO-KUN</au><au>RATH DAVID L</au><au>TSENG WEI-TSU</au><au>CHEN SHYNG-TSONG</au><au>RUBINO JUDITH M</au><au>NARAYAN CHANDRASEKHAR</au><au>SAENGER KATHERINE L</au><au>JAMIN FEN F</au><au>LOFARO MICHAEL F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Copper recess process with application to selective capping and electroless plating</title><date>2004-06-17</date><risdate>2004</risdate><abstract>An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Copper recess process with application to selective capping and electroless plating |
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