Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures

In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable...

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Hauptverfasser:	CHIRAS STEFANIE RUTH, ROSENBERG ROBERT, LANE MICHAEL WAYNE, MC FEELY FENTON REED, SAMBUCETTI CARLOS JUAN, MALHOTRA SANDRA GUY, VEREECKEN PHILIPPE MARK
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	CHIRAS STEFANIE RUTH ROSENBERG ROBERT LANE MICHAEL WAYNE MC FEELY FENTON REED SAMBUCETTI CARLOS JUAN MALHOTRA SANDRA GUY VEREECKEN PHILIPPE MARK
description	In integrated circuit technology; an electromigration and diffusion sensitive conductor of a metal such as copper and processing procedure therefore is provided, wherein, at a planarized chemical mechanical processed interfacing surface, the conductor metal is positioned in a region of a selectable low K eff dielectric material surrounded by a material selected to be protection from outdiffusion and a source of a film thickness cap that is to form over the conductor metal and/or serve as a catalytic layer for electroless selective deposition of a CoWP capping layer.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures
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