Apparatus and method for automated transistor and component folding to produce cell structures

A method for generating an integrated circuit layout is disclosed. One embodiment includes receiving an integrated circuit netlist describing a plurality of transistors and a plurality of conductors for interconnecting the plurality of transistors, each of the plurality of transistors having a width...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MCGUINNESS PATRICK JAMES, GOLIKOV MICHAEL VIACHESLAVOVICH, MARCHENKO ALEXANDER MIKHAILOVICH, MAZIASZ ROBERT LEE, ROZENFELD VLADIMIR PAVLOVICH, ZINCHENKO ANDREI VLADIMIROVITCH
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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