Pseudostatic memory circuit
A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first oper...
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creator | JAKOBS ANDREAS MENKE MANFRED JANIK THOMAS PLATTNER ECKEHARD |
description | A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area. |
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The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.</description><edition>7</edition><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040408&DB=EPODOC&CC=US&NR=2004066686A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25566,76549</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20040408&DB=EPODOC&CC=US&NR=2004066686A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JAKOBS ANDREAS</creatorcontrib><creatorcontrib>MENKE MANFRED</creatorcontrib><creatorcontrib>JANIK THOMAS</creatorcontrib><creatorcontrib>PLATTNER ECKEHARD</creatorcontrib><title>Pseudostatic memory circuit</title><description>A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOKE4tTckvLkksyUxWyE3NzS-qVEjOLEouzSzhYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBgYmBmZmZhZmjobGxKkCAC-2JMY</recordid><startdate>20040408</startdate><enddate>20040408</enddate><creator>JAKOBS ANDREAS</creator><creator>MENKE MANFRED</creator><creator>JANIK THOMAS</creator><creator>PLATTNER ECKEHARD</creator><scope>EVB</scope></search><sort><creationdate>20040408</creationdate><title>Pseudostatic memory circuit</title><author>JAKOBS ANDREAS ; MENKE MANFRED ; JANIK THOMAS ; PLATTNER ECKEHARD</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004066686A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>JAKOBS ANDREAS</creatorcontrib><creatorcontrib>MENKE MANFRED</creatorcontrib><creatorcontrib>JANIK THOMAS</creatorcontrib><creatorcontrib>PLATTNER ECKEHARD</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JAKOBS ANDREAS</au><au>MENKE MANFRED</au><au>JANIK THOMAS</au><au>PLATTNER ECKEHARD</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Pseudostatic memory circuit</title><date>2004-04-08</date><risdate>2004</risdate><abstract>A memory circuit, in particular a psuedostatic memory circuit, is selected by a memory selection signal. The memory circuit has memory areas and a control circuit in order to refresh a memory area of the memory circuit in accordance with a refresh request signal. The control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the memory circuit is deselected or if, in the event of selection of the memory circuit by the memory selection signal, the access to the memory area is ended before the generation of a further refresh request signal. The control circuit, in a second operating mode, interrupts an access to the memory area for the writing and read-out of data and carries out a refresh of the memory area by generation of a refresh signal if the memory circuit is selected and a further refresh request signal is received before the ending of the access to the memory area.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Pseudostatic memory circuit |
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