Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate

Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate

A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic cou...

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Hauptverfasser: MULLINS TIMOTHY JOHN, KOSSMAN HAROLD F
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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KOSSMAN HAROLD F
description A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004059896A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004059896A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004059896A13</originalsourceid><addsrcrecordid>eNqNjLsKwkAQRdNYiPoPA9aB-MSUIoqNlVqHYXeSXdzHsDshv29EP8DicuBwuNPC3khM1IBhHDMmlD5DGxNYz448BbGhAxliKZYSaRCTCDVkQSHwvRP7NZ8s98wxCQyjA2M7A8pF9YLxlebFpEWXafHjrFhezo_TtSSODWVGRYGked7XVbWtdvWh3h9Xm_-qN6vjQl4</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><source>esp@cenet</source><creator>MULLINS TIMOTHY JOHN ; KOSSMAN HAROLD F</creator><creatorcontrib>MULLINS TIMOTHY JOHN ; KOSSMAN HAROLD F</creatorcontrib><description>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040325&amp;DB=EPODOC&amp;CC=US&amp;NR=2004059896A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040325&amp;DB=EPODOC&amp;CC=US&amp;NR=2004059896A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MULLINS TIMOTHY JOHN</creatorcontrib><creatorcontrib>KOSSMAN HAROLD F</creatorcontrib><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><description>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLsKwkAQRdNYiPoPA9aB-MSUIoqNlVqHYXeSXdzHsDshv29EP8DicuBwuNPC3khM1IBhHDMmlD5DGxNYz448BbGhAxliKZYSaRCTCDVkQSHwvRP7NZ8s98wxCQyjA2M7A8pF9YLxlebFpEWXafHjrFhezo_TtSSODWVGRYGked7XVbWtdvWh3h9Xm_-qN6vjQl4</recordid><startdate>20040325</startdate><enddate>20040325</enddate><creator>MULLINS TIMOTHY JOHN</creator><creator>KOSSMAN HAROLD F</creator><scope>EVB</scope></search><sort><creationdate>20040325</creationdate><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><author>MULLINS TIMOTHY JOHN ; KOSSMAN HAROLD F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004059896A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MULLINS TIMOTHY JOHN</creatorcontrib><creatorcontrib>KOSSMAN HAROLD F</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MULLINS TIMOTHY JOHN</au><au>KOSSMAN HAROLD F</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate</title><date>2004-03-25</date><risdate>2004</risdate><abstract>A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-24T09%3A10%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MULLINS%20TIMOTHY%20JOHN&rft.date=2004-03-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2004059896A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true