Method and apparatus for transferring data between a source register and a destination register

A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are pa...

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Hauptverfasser: RIZI HAIM, GUR AMIT, HALAHMI DROR
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creator RIZI HAIM
GUR AMIT
HALAHMI DROR
description A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2004014427A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2004014427A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2004014427A13</originalsourceid><addsrcrecordid>eNqNi7EKwkAQBdNYiPoPC9ZCEg-sRRQbK7UOa_ISD2Tv2N3g7yso1haPKWbetGhO8HvqiOW9nFnZR6M-KbmyWA_VKAN17Ew3-BMQYrI0agtSDNEc-nlTB_Mo7DHJT82LSc8Pw-LLWbE87C-74wo5NbDMLQTeXM91WYayCqHebKv1f9ULgtQ-AQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method and apparatus for transferring data between a source register and a destination register</title><source>esp@cenet</source><creator>RIZI HAIM ; GUR AMIT ; HALAHMI DROR</creator><creatorcontrib>RIZI HAIM ; GUR AMIT ; HALAHMI DROR</creatorcontrib><description>A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040122&amp;DB=EPODOC&amp;CC=US&amp;NR=2004014427A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040122&amp;DB=EPODOC&amp;CC=US&amp;NR=2004014427A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RIZI HAIM</creatorcontrib><creatorcontrib>GUR AMIT</creatorcontrib><creatorcontrib>HALAHMI DROR</creatorcontrib><title>Method and apparatus for transferring data between a source register and a destination register</title><description>A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwkAQBdNYiPoPC9ZCEg-sRRQbK7UOa_ISD2Tv2N3g7yso1haPKWbetGhO8HvqiOW9nFnZR6M-KbmyWA_VKAN17Ew3-BMQYrI0agtSDNEc-nlTB_Mo7DHJT82LSc8Pw-LLWbE87C-74wo5NbDMLQTeXM91WYayCqHebKv1f9ULgtQ-AQ</recordid><startdate>20040122</startdate><enddate>20040122</enddate><creator>RIZI HAIM</creator><creator>GUR AMIT</creator><creator>HALAHMI DROR</creator><scope>EVB</scope></search><sort><creationdate>20040122</creationdate><title>Method and apparatus for transferring data between a source register and a destination register</title><author>RIZI HAIM ; GUR AMIT ; HALAHMI DROR</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2004014427A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION</topic><toplevel>online_resources</toplevel><creatorcontrib>RIZI HAIM</creatorcontrib><creatorcontrib>GUR AMIT</creatorcontrib><creatorcontrib>HALAHMI DROR</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RIZI HAIM</au><au>GUR AMIT</au><au>HALAHMI DROR</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for transferring data between a source register and a destination register</title><date>2004-01-22</date><risdate>2004</risdate><abstract>A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION
title Method and apparatus for transferring data between a source register and a destination register
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T12%3A17%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RIZI%20HAIM&rft.date=2004-01-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2004014427A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true