Sacrificial inlay process for improved integration of porous interlevel dielectrics
A nonporous sacrificial layer is used to form conductive elements such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth...
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creator | ADEM ERCAN ERB DARRELL M |
description | A nonporous sacrificial layer is used to form conductive elements such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth walled conductive elements, the sacrificial layer is removed and replaced with a porous dielectric, resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials. |
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After formation of the smooth walled conductive elements, the sacrificial layer is removed and replaced with a porous dielectric, resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials.</description><edition>7</edition><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2003</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031127&DB=EPODOC&CC=US&NR=2003219968A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20031127&DB=EPODOC&CC=US&NR=2003219968A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ADEM ERCAN</creatorcontrib><creatorcontrib>ERB DARRELL M</creatorcontrib><title>Sacrificial inlay process for improved integration of porous interlevel dielectrics</title><description>A nonporous sacrificial layer is used to form conductive elements such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth walled conductive elements, the sacrificial layer is removed and replaced with a porous dielectric, resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2003</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNissKwkAMRbtxIeo_BFwLfYDYpYjifnRdwjQjgXEyJGPBv7eIH-Dqcs65y8o59MqBPWMEThHfkFU8mUEQBX7ONNE4p0IPxcKSQAJkUXnZ12qkiSKMTJF8Ufa2rhYBo9Hmt6tqeznfTtcdZRnIMnpKVIa7a-u6a5u-3x-OTfff6wOy2Dpn</recordid><startdate>20031127</startdate><enddate>20031127</enddate><creator>ADEM ERCAN</creator><creator>ERB DARRELL M</creator><scope>EVB</scope></search><sort><creationdate>20031127</creationdate><title>Sacrificial inlay process for improved integration of porous interlevel dielectrics</title><author>ADEM ERCAN ; ERB DARRELL M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2003219968A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2003</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ADEM ERCAN</creatorcontrib><creatorcontrib>ERB DARRELL M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ADEM ERCAN</au><au>ERB DARRELL M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Sacrificial inlay process for improved integration of porous interlevel dielectrics</title><date>2003-11-27</date><risdate>2003</risdate><abstract>A nonporous sacrificial layer is used to form conductive elements such as vias or interconnects in an inlay process, resulting in smooth walled structures of the inlaid vias or interconnects and smooth walled structures of any surrounding layers such as barrier layers. After formation of the smooth walled conductive elements, the sacrificial layer is removed and replaced with a porous dielectric, resulting in desirable porous low-k dielectric structures integrated with the smooth walled conductive elements and barrier materials.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Sacrificial inlay process for improved integration of porous interlevel dielectrics |
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