SELF TIMED PRE-CHARGED ADDRESS COMPARE LOGIC CIRCUIT

An Address Compare Circuit (1) allows for a large compare function at high speed due to its unique self-timed evaluation clock and bit compare circuits. The address compare circuit can reliably self-time off of the input data which insures proper compare timing with respect to the arrival of two address busses being compared. The HIT evaluation clock is generated by a circuit that has additional control inputs to increase the arrival times of input data, resulting in a greater operating window. This circuit provides a way to generate a very accurate internal HIT evaluation clock; therefore, the compare circuit reduces the extra setup time needed to guarantee all address data bits are valid. Furthermore, the HIT evaluation clock can be delayed to increase the arrival times of input data, resulting in a greater operating window.