Semiconductor device array having dense memory cell array and hierarchical bit line scheme

A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an "open" configuration, allowing adjacent unit circuits (202) be...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	OGATA YOSHIHIRO
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!