Method and system for handling multiple bit errors to enhance system reliability

The present invention provides an improved method, an system, and a set of computer implemented instructions for handling a cache containing multiple single-bit hard errors on multiple addresses within a data processing system. Such handles will prevent any down time by logging in the parts to be re...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	REICK KEVIN F, LEMMON WAYNE, LEWIS DAVID OTTO, FIELDS JAMES STEPHEN, KITAMORN ALONGKORN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!