Single poly EEPROM with reduced area and method of making same

An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate co...

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Hauptverfasser:	MITROS JOZEF C, SPRINGER LILY, BUCKSCH ROLAND
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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