Multiple level built-in self-test controller and method therefor

An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpr...

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Bibliographische Detailangaben

Hauptverfasser:	COOK BRIAN E, YAP ALEX S, JENSEN ROBERT A, AURORA MARK S, LEDFORD JAMES S
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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